Abstract: A low dielectric constant fluorinated polyimide hasbeen employed as the interlevel dielectric in afour-level metal VLSI process. Due to the stringentrequirement of a near global planar topography comparedwith the partial planarizing properties of thepolyimide, two advanced approaches were evaluated: (1)a `negative-image' sacrificial photoresist etchbackprocess, and (2) a photoresist image reversal plus dryetch process. Both techniques remove the polyimide fromthe surface of the metal while leaving polyimide`islands' or `plugs' between the metal features. Asecond polyimide layer is then applied. The planarityof the finished structure is controlled by thethickness of the initial polyimide layer, the plasmaetch process, and the planarizing characteristics ofthe second or `recoat' polyimide film. The improvedglobal planarity achievable using the advancedtechniques were compared to a standard single spinpolyimide process using surface profilometer profilesand cross-sectional SEM micrographs. The pros and consof the two planarization techniques are also discussed.!12
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